The present invention relates to microprocessor bus controllers and in particular to bus controllers incorporating state machine technology to provide a functional link between microprocessors having different size data widths, and a data bus which allows access to devices having different size data widths on the data bus.
In a microprocessor controlled computer system such as a personal or desk top computer, the computer requires a set of electronic connections between the microprocessor and other devices making up- the computer system. These communication lines are collectively called the input/output system or I/O bus. All messages in data pass between the microprocessor and other system components travel on the bus. A complete I/O bus includes several component parts: the data bus, lines over which data flows; the address bus, a set of lines that specify the memory addresses to which data will be transferred; and various support lines carrying control signals and power for the various devices on the bus. A bus controller initiates and controls all I/O bus cycles. The controller controls the interface to the I/O bus, the address and data buffers, the CPU, the direct memory access (DMA) device and other memory controllers.
Prior art bus controllers were integrated into and functioned as a part of the microprocessor architecture. As microprocessor technology has advanced, bus controller technology has become separate and distinct. Similarly, as the number of peripheral devices available for use with various microprocessors has increased, it has become obvious that peripheral devices usable with one integrated microprocessor-bus controller architecture can not generally be used with the bus controller of another microprocessor.
Separate microprocessor and bus controller architectures provide system design flexibility as well as facilitating interface of many peripheral devices among many different microprocessors. In the present state of the art, microprocessors are expected to interface with memory manage units, CRT controllers, floppy disc controllers, hard disc controllers, arithmetic cove processors and the like. In addition, it is well known that the next generation of 32-byte microprocessors must be able to interface with already existing peripheral devices without the immediate need for specifically designed bus controllers.
However, even though the present day microprocessor and bus controller architectures are separated, bus controllers designed to interface with a specific type or range of types of microprocessors and peripheral devices are still limited to certain system configurations and further limit design flexibilitas for the next generation of microprocessors. See for example the well-known personal computer models known as the "PC XT" and "PC AT", manufactured and marketed by the IBM Corporation.
In the past, I/O bus structures and small microprocessor based computer systems comprised little more than buffered extensions of the microprocessor I/O pins. While microprocessors speeds, data widths, architecture and I/O protocols evolve at a rapid rate, system level I/O bus configurations remain essential unchanged in structure and timing for five to ten years. For example, reflecting the capabilities of its 8-bit 8088 microprocessor, the original IBM PC utilizes an I/O bus which permits only eight bits of data to be transferred at one time. With the more advanced PC AT, while maintaining the simplicity in functionality of the original PC I/O bus, IBM added an additional 8 data lines to the I/O bus to provide for 16-bit data transfers. More recently, new more sophisticated I/O buses having greater capabilities have been developed; for example, the IBM "Micro Channel" I/O bus developed for IBM's new "PS/2" computer models. IBM's basic micro-channel design supports 8-bit data transfers with additional pins provided for 16- and 32-bit operations. The biggest advantage of the new micro-channel type I/O buses, is their "multiple master architecture" which allows microprocessors on expansion boards to have full access to the computer system's resources. In order to achieve capabilities and functionality of the new buses, a bus controller is required which automatically accommodates one or more microprocessors, which may have different word or data widths and which allows the microprocessors to access other devices, "slaves", on the bus which may have different data width sizes from each other and from the microprocessors.